标题: 10nm at TSMC, Intel [打印本页] 作者: choi 时间: 7-5-2015 10:55 标题: 10nm at TSMC, Intel (1) 小島 郁太郎, 10nm FinFETの設計フローはここまできた、TSMCが講演. NikkeiBP (for "Nikkei Business Publications, Inc"), July 3, 2015. http://techon.nikkeibp.co.jp/art ... T=edaonline&P=1
translation:
(a) the title: design flow of 10nm FinFET started from here.
(b) the text: TSMC in a speech disclosed early arrival of both 16nm FinFET＋ (N16FF＋) process and 10nm FinFET (N10FF) process. For example, N10FF first tapeout is on quad-core ARM Cortex-A57. This speech was delivered at "Collaborating to Enable Design with 16-nm and 10-nm FinFET" (an June 8, 2015 event co-sponsored US-based Synopsys, England-headquartered ARM and Taiwan's TSMC)--[a seminar held on the sidelines of] in a hotel close to "52nd Design Automation Conference（DAC 2015）." The speaker was TSMC's Willy Chen.
(2) Read (b)--not (a).
(a) Jeremy Quach, Biz Break: Intel suffers triple whammy: Downgrade, delays, layoffs. San Jose Mercury News, June 26, 2015 http://www.mercurynews.com/60-se ... my-downgrade-delays
("Intel's successor to Skylake, [successor codenamed] Canonlake, was expected to be released in 2016, then was delayed to 2017, is now on hold indefinitely, indicating that Intel has been struggling with the 10nm processor. The Skylake processor will now be succeed by Kaby Lake processors, a much smaller upgrade than originally expected")
, which cited
Martin Blanc, Intel Corporation 10nm Cannonlake Chips Facing Delays; Kaby Lake To Debut Next Year. Bidness Etc, June 26, 2015. www.bidnessetc.com/46362-intel-c ... y-lake-to-debut-ne/
(b) HOWEVER, you should not read either of the aforementioned report, because they SEEMINGLY (sharing the same words, for instance) came from