Samsung to Take on TSMC in Chip-Packaging Technology

choi

(1) Lee Min-hyung, Samsung to Take on TSMC in Chip-Packaging Technology. Korea Times, June 14, 2016.
http://www.koreatimes.co.kr/www/news/tech/2016/06/133_206979.html

Quote:

"Samsung Electro-Mechanics [a subsidiary separate from the chip-making Samsung Electronics] has developed a new chip-packing technology * * * a type of Fan-Out Wafer Level Package (FoWLP) * * * If smartphone makers adopt the FoWLP-based application processors for their new handset, they can reduce the thickness by more than 0.3 millimeters and improve the general efficiency of the handset by more than 30 percent, according to the report [by Hana Financial Investment].

" 'We expect Samsung to start mass-producing the FoWLP-embedded chips as early as the first half of next year, which we believe is not too late, compared to the third quarter this year of TSMC,' said the [Hana] report.

Note: The nature of Fan-Out Wafer Level Package, and its significance, will be explained hereafter.

(2) David Lammers, Fan-Out is a Game Changer. In Nanochip Fab Solution; Solutions for factory and equipment efficiency: Packing more into less. Applied Materials, December 2015.
http://www.appliedmaterials.com/ ... t-is-a-game-changer

Quote:

"In a financial results conference call with analysts in mid-October, TSMC co-CEO Mark Liu said TSMC's InFO technology 'will enter high-volume production with our 16-nanometer technology next year [in (1), quotation 2: 'third quarter this year of TSMC']. We are currently working on the second-generation InFO technology for several projects of systems integration on 10 nanometer and 7 nanometer.'

"First developed independently by Freescale and Infineon some 15 years ago, and subsequently licensed and developed by multiple OSATs [OSAT: Outsourced Semiconductor Assembly and Test, one of which is ASE, Advanced Semiconductor Engineering 日月光], fan-out packaging is starting to see volume production.

Note: The equipment maker, Applied Materials, publishes a periodical "Nanochip Fab Solution; Solutions for factory and equipment efficiency" four times a year (Apr, July, Sept and Dec). Each issue has a topic, and the Dec 2015 issue deals with "Packing more into less" that appeared in the cover.

choi

(4) fan in and fan out
(a) Shichun Qu and Yong Liu, Wafer-Level Chip-Scale Packaging; Analog and power semiconductor applications. Springer, 2015.
https://books.google.com/books?i ... eginner&f=false
(at page 4: "section 1.3 Fan-In Versus Fan-Out * * * This has been made possible by a significant miniaturization of the chip package. WLCSPs [WLCSP: wafer-level chip-scale packaging] are manufactured before wafer dicing and enable further form factor reduction and allow saving cost particularly when packaging small dice; it can be divided into two categories [17]: fan-in wafer-level packaging and fan-out wafer-level packaging. True wafer-level packages are inevitably fan-in packages. This means that their contact terminals are all within the footprint of the die. This translates into a severe limitation for adjusting the layout of the contact terminals to match the design of the next-level substrate (printed circuit board, interposer, IC package). Fan-out wafer-level packages represent a comprise between  die-level packaging and wafer-level packaging. In both fan-in and fan-out cases, no laminate substrate or epoxy mold compound is needed to connect the die to the PWB (such as underfill). Solder balls are directly attached onto the silicon die and/or the fan-out area")
(i) printed circuit board
https://en.wikipedia.org/wiki/Printed_circuit_board
("When the board has no embedded components it is more correctly called a printed wiring board (PWB) or etched wiring board. However, the term printed wiring board has fallen into disuse")
(ii) In the book above, go next to Figure 2.1 at page 16, and you will immediately understand the meaning of the quotation.

(b) The quotation of the book above actually talks about 2-D WLCSP. The following book deminstrates both 2- and 3-D WLCSP.

Ron Huemoeller and Curtis Zwenger (both of Ankor Technology), Silicon Wafer Integrated Fan-Out Tachnology. ChipScaleReview.com, March/ April, 2015.
file:///C:/Users/cm-00_0a_e4_1b_80_6e/Downloads/SiliconWaferIntegratedFanoutCSRMarApril2015.pdf
(Figure 3 captio: "3D WLFO PoP [package-on-pacjagw] package structure")

choi

(3)
(a) wafer-level packaging
https://en.wikipedia.org/wiki/Wafer-level_packaging
("Wafer-level packaging (WLP) is the technology of packaging an integrated circuit while still part of the wafer, in contrast to the more conventional method of slicing the wafer into individual circuits (dice) and then packaging them. WLP is essentially a true chip-scale package (CSP) [click it and it says, 'Originally, CSP was the acronym for chip-size packaging'] technology, since the resulting package is practically of the same size as the die")

(b) die/dice
(i) wafer (electronics)
https://en.wikipedia.org/wiki/Wafer_(electronics)
(section 4.2 Analytical die count estimation: dies always have a square or rectangular shape due to the constraint of wafer dicing [the illustration, and its caption, leaves no doubt that a die is a chip])
(ii) die (integrated circuit)
https://en.wikipedia.org/wiki/Die_(integrated_circuit)
("There are three commonly used plural forms: dice, dies, and die.[1][2]")