Finfet

choi

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John Markoff, To Enhance Chip Speed, Intel Enters Third Dimension. New York Times, May 5, 2011.
http://www.nytimes.com/2011/05/05/science/05chip.html?_r=1&scp=1&sq=INTEL%20dimension&st=cse
("Intel is on track for 22-nanometer manufacturing later this year" with the Finfet 3-D design)

Note:
(a) Wall Street Journal today puts it "early 2012."
(b) David Manners, TSMC waiting till 20nm to introduce 3D transistors. ElectronicsWeekly, May 5, 2011.
http://www.electronicsweekly.com/Articles/2011/05/05/51013/tsmc-waiting-till-20nm-to-introduce-3d-transistors.htm

Dow Jones puts it 2013.
Lorraine Luk, TSMC: Won't Adopt 3-D Transistors Before 2-D Technology Exhausted. Dow Jones, May 5, 2011.
http://online.wsj.com/article/BT-CO-20110505-701752.html
("TSMC, the world's largest contract chip manufacturer by revenue, produces chips using 28-nanometer technology and plans to migrate to the more advanced 20-nanometer technology in 2013")
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