TechInsights Finds SMIC 7nm (N+2) in Huawei Mate 60 Pro

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TechInsights Finds SMIC 7nm (N+2) in Huawei Mate 60 Pro. TechInsights, Sept 4, 2023
https://www.techinsights.com/blo ... -huawei-mate-60-pro

Note:
(a)
(i) The report is free.
(ii) This report confirms what Bloomberg reported first (a day ago), which also did the teardown.
(b) About TechInsights. TechInsights, undated.
https://www.techinsights.com/about-techinsights
(address: 1891 Robertson Rd #500, Nepean, ON K2H 5B7)

Quote:

"Every year, TechInsights analyzes 750+ advanced technology products, catalogues 6,500+ components, and analyzes 2,000+ chips. We maintain the world’s largest database of semiconductor and technology analysis.

"Founded in 1989 in Ottawa, Canada, TechInsights first appeared on the semiconductor scene as Semiconductor Insights when a small reverse engineering group was spun out from a [Dram] memory design company [Mosaid (founded in Ottawa and remains there: en.wikipedia.org), which spin out the predecessor in 1989].

* Nepean was an independent city that became part (as a neighborhood) of Ottawa in 2001.
(c) "Huawei Mate 60 Pro" does not have a Chinese name.
(d) "The Kirin 9000s die measured 107 mm2"
(i) Kirin 9000s   麒麟 9000s
(ii) ie (integrated circuit)
https://en.wikipedia.org/wiki/Die_(integrated_circuit)
("The wafer is cut (diced) * * * Each of these pieces is called a die.   There are three commonly used plural forms: dice, dies, and die")

(e) "Initial lab results indicated that this die is more advanced than SMIC's 14nm process node but presents larger critical dimensions (CDs) than what TechInsights has observed for 5nm process."
(i) The "critical dimension" here literally means process node. The clause "presents larger critical dimensions (CDs) than what TechInsights has observed for 5nm process" simply means it is not 5 nm, but more.
(A) photolithography
https://en.wikipedia.org/wiki/Photolithography
, whose section 5 (sectional heading: Resolution in projection systems) displays an equation, which includes CD or "critical dimension." You need not learn more, because this Wiki page does not explain well. See the next two immediately.
(B) Scott Middlebrooks, The Rayleigh Criterion; The resolution equation that determines just how small the features on a chip can be printed. ASML, undated
https://www.asml.com/en/technolo ... /rayleigh-criterion
("Smaller critical dimension can be achieved by using a combination of smaller light wavelength and larger numerical aperture (NA), while pushing k1 as close as possible to the physical limit"_

Who was this Rayleigh? Angular resolution
https://en.wikipedia.org/wiki/Angular_resolution
(section 2 The Rayleigh criterion: Lord Rayleigh [1842 – 1919])

Not to be confused with Raleigh, North Carolina
https://en.wikipedia.org/wiki/Raleigh,_North_Carolina
("The city of Raleigh is named after Sir Walter Raleigh [c 1552 – 1618], who established the now-lost Roanoke Colony in present-day Dare County")

As you can imagine, the ay (pronounced the same as ay in ray) in Rayleigh is pronounced differently from that a in Raleigh.
(C) Sander Hofman, What Is a Gate-All-Around Transistor?  ASML, Oct 3, 2022.
https://www.asml.com/en/news/sto ... l-around-transistor

Quote:

# "One of the most talked-about transistor designs is the gate-all-around transistor, which TSMC, Samsung and Intel have all announced they will be using in the coming years." (That is the future. The next is about truth in general.)

# "What is a transistor?
A transistor is a semiconductor component that amplifies or switches electrical signals. It’s one of the building blocks of modern electronics, including chips. Most of today's chips contain billions of transistors.

"How do transistors work?
Transistors make up the basic fabric of a chip. All transistors are interconnected and act as switches for electrical current. These gates turn on and off, either allowing or preventing current from passing through. This means that each transistor can be in two different states, storing two numbers – zero and one. With billions of transistors, a chip can contain billions of zeros and ones, sending, receiving and processing a remarkable amount of digital data. Just like any switch, a transistor needs to do three things exceptionally well: allow the maximum amount of current to flow through when its on, allow little to no current to leak when it’s off, and switch on and off as quickly as possible to guarantee optimal performance.

(ii) Reinforcement of critical dimension is process node, which is the width of gate that electric current pass through from "source" to "drain" (in that direction).

Nerissa Draeger, Scaling Up And Down. Semiconductor Engineering, Oct 21, 2019
https://semiengineering.com/scaling-up-and-down/
("Transistor Scaling[:]
The phenomenon of semiconductor scaling has a particularly famous description: Moore's Law. Originally meant as an economic observation, it predicts the doubling of chip component densities every 2 years. For decades, the industry kept on track by shrinking a key (or 'critical') component dimension through advances in lithography and plasma etching – the processes by which a pattern is defined on the wafer surface and transferred into the underlying material. That critical dimension was frequently the transistor gate length dimension. For example, the 0.5 µm technology node produced a transistor with 0.5 µm gate length. Over the years, the technology node definition has evolved and is now considered more of a generational name rather than a measure of any key dimension. What remains the same is our expectation that node scaling will bring better device performance and greater power efficiency and cost less to build")

(f) Let's return to the dawn of integrated circuit (IC). There was no 3-dimensional (such as fin field-effect transistor (FinFET)). Only photolithography.
(i) 1959: Invention of the "Planar" Manufacturing Process; Jean Hoerni develops the planar process to solve reliability problems of the mesa transitor, thereby revolutionizing semiconductor manufacturing.. Mountain View, California: Computer History Museum (CHM), undated.
https://www.computerhistory.org/ ... ufacturing-process/
(A) Jean Hoerni
https://en.wikipedia.org/wiki/Jean_Hoerni
(1924 – 1997; Swiss-American)
(B) Return to Note (e)(i)(A):
https://en.wikipedia.org/wiki/Photolithography
, whose section 4 Photomasks provides the concept of oxide as photomask in manufacturing process.  
(C) The Silicon Dioxide Solution; How Physiciast Jean Hoerni built the bridge from the transistor to the integrated circuit. IEEE Spectrum, Dec 1, 2007.
https://spectrum.ieee.org/the-silicon-dioxide-solution
(ii) Fairchild's Approach: The Planar Process. CHM, undated.
https://www.computerhistory.org/revolution/digital-logic/12/329

(g) "“Discovering a Kirin chip using SMIC's 7nm (N+2) foundry process in the new Huawei Mate 60 Pro smartphone demonstrates the technical progress China's semiconductor industry has been able to make without EUV lithography tools."
(i)
(A) press release: China's Chipmaking Giant SMIC's N+1 process Makes Tape-out Breakthrough. China.org.cn, Oct 15, 2020.
https://www.prnewswire.com/il/ne ... ough-815606605.html

Quote:

# "China's chip customization solution provider Innosilicon announced on Oct. 11 that it has taped-out and completed testing of a prototype chip based on Semiconductor Manufacturing International Corporation (SMIC)'s FinFET N+1 process, raising the morale in China's foundry industry.

"N+1, SMIC's new generation foundry node, is said to be comparable to the 7nm process by Taiwan Semiconductor Manufacturing Company (TSMC), world's largest dedicated independent semiconductor foundry. Tape-out is the final phase of a chip's development before manufacturing starts, and this specific achievement marks another step forward in China's homegrown chip development.

# "Liang Mengsong [梁孟松, whose does not hold US citizenship or permanent residency], co-CEO of SMIC, said the N+1 7nm node is a significant improvement over its current 14nm production node, boasting a 20% increase in performance, power consumption reduction of 57%, a reduced logic area by 63%, and SoC (System on a Chip) area reduction by 55%.

"But compared with the improvement standard of 35% in the industry, its performance improvement of 20% is not enough, so the N+1 process is for low-power applications, Liang said. In the future, an N+2 process of higher performance improvement, higher cost and similar power consumption will be developed, he added.

(B) Russian Government's New Semiconductor Plan: 28nm Local by 2030. Compound Semiconductor News, Apr 16, 2022
https://www.csfusion.org/semicon ... 28nm-local-by-2030/

two consecutive Q&As:

"Who can produce 7nm chips?
In April 2018, TSMC announced volumetric production of 7 nm (CLN7FF, N7) chips. In June 2018, the company announced an increase in mass production. In May 2018, Samsung announced the production of 7 nm (7LPP) chips this year. ASML Holding NV is their main supplier of EUV lithography machines.

"Can SMIC produce 7nm?
The breakthrough in FinFET also provided a basis for SMIC to develop its 'N 1,' 'N 2' and 7 nm process nodes. As previously noted by SMIC, its 14 nm process reached volume production in the fourth quarter of 2019, and N 1 pilot production also started at the end of 2020.

(ii) "without EUV lithography tools" where EUV stands for extreme UV. The EUV tools are in the domain of ASML, based in the Netherlands.